The present invention relates to a method of manufacturing a MOS semiconductor device and, more particularly, to a method of manufacturing a MOS integrated semiconductor device.
In the manufacture of a MOS transistor, a diffusion region (or a well region) may sometimes be formed in the surface area of a semiconductor substrate, in order to facilitate the control of MOS transistor's characteristics. The source and drain regions of the MOS transistor are formed in the surface area of the well region. The threshold voltage of the MOS transistor varies in response to the impurity concentration (or carrier density) of a channel region between the source and drain regions. It is already known that the characteristics of the MOS transistor are improved when the impurity concentration of the well region decreases in the vicinity of the surface.
In the conventional method of manufacturing a number of MOS transistors, there are disadvantages, as will be described, in the integration of the MOS transistors in a single semiconductor substrate. In the integration, a field oxide layer is used to electrically separate the MOS transistors sufficiently from each other.
The conventional method of manufacturing MOS transistors will now be described with reference to FIGS. 1A to 1C. In FIGS. 1A to 1C, the formation of a MOS transistor is shown for simplicity of description, but a plurality of MOS transistors are actually formed simultaneously through the steps of FIGS. 1A to 1C. In the manufacturing method, n-type silicon substrate 10, for example, is initially prepared, and resist pattern 12 is then formed thereon. Then, a p-type impurity is ion-implanted into substrate 10, using pattern 12 as a mask, and further activated by annealing in order to form p-type well region 14. After the formation of well region 14, the n-type impurity is ion-implanted into region 14, using pattern 12 as a mask, thereby forming ion-implanted region 14A, as shown in FIG. 1A. Region 14A has a reduced carrier density in the vicinity of the surface of region 14, without inverting the conductivity type.
Field oxide layer 16, shown in FIG. 1B, is formed by the selective thermal oxidation of the surfaces of substrate 10 and region 14 after the step of FIG. 1A. Layer 16 surrounds part of the surface of region 14. The surrounded part is used as an element region. The exposed surface of region 14 is covered with gate oxide film 18. Gate electrode 20, shown in FIG. 1C, is formed on film 18. After the formation of electrode 20, then n-type impurity is further ion-implanted into region 14, using electrode 20 and layer 16 as masks, as shown in FIG. 1C. The implanted impurity is then activated by annealing, thereby forming n.sup.+ -type source and drain regions 22A and 22B, as shown in FIG. 1C. Thus, the formation of the MOS transistor is completed.
In the aforementioned manufacturing method, resist pattern 12 is commonly utilized in the ion implantation process, for forming p-type well 14, and for forming ion-implanted region 14A. Thus, when field oxide layer 16 is formed, the n-type impurity in region 14A is thermally diffused. This diffusion undesirably reduces the carrier density of that part of region 14 which is located directly under layer 16. In this case, layer 16 cannot sufficiently insulate the MOS transistors from each other. More specifically, since the wiring layers of the MOS transistors are formed above layer 16, if the carrier density directly under layer 16 is decreased, an significant amount of leakage current may flow, due to an electric field emitted from the wiring layers.
Further, the n-type impurity in region 14A is exceedingly diffused by heat during the formation of layer 16. Therefore, it is difficult to set the channel length of the MOS transistors to be sufficiently short.